A Tlm-based Network-on-chip Performance Evaluation Framework

The variety of interconnection structures presently nowadays for SoC (System-on-Chip), bus and networkson-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application at the firsts stages of the SoC design. The present study aims to enhance the SoC communication platform design area, when a Networkon-Chip NoC is used. The novelty of this work is the performance evaluation of different NoC configuration at firsts stages of the SoC design flow (SystemC TLM). For evaluating the NoC a monitoring process was carried on. Our approach employed a set of metrics for NoC to elucidate the global and inner NoC behavior under a wide variety of traffic conditions.